The increasing further developments of computer and telecommunications systems as well as peripheral equipment also require continuously increasing processor power and data transfer rates, to the same extent. Thus, for example, the amounts of data that are becoming ever larger for the transmission of images, speech and music via a network, such as the Internet, require very high data transmission rates and very high processor power levels. Further development of both the hardware components and of the software of such systems is thus a significant factor in order to make it possible to comply with the demanded requirements. The interfaces in computer or telecommunications systems such as these must, in particular, be continuously developed further in order to make it possible to transmit the large amounts of data as effectively and efficiently as possible between the modules of the system.
One interface that is known in computer and telecommunications systems is the UART interface (Universal Asynchronous Receiver and Transmitter). A UART interface such as this or a UART module such as this allows serial asynchronous data transmission, and is a module which allows serial and bit-oriented communication in a telecommunications system or in a computer system. The UART module allows the conversion of characters, which are received in parallel from the memory, to bit-oriented data streams using a specific protocol format and allows the opposite procedure on reception of data.
During the course of the development of such UART modules, three functional types have been created, which are referred to as unbuffered UART modules, as buffered UART modules and as DMA (Direct Memory Access) UART modules. The method of operation of unbuffered UART modules can be described as follows. In order to transmit a character, the character is stored by the processor unit (CPU=Central Processing Unit) in a hold register. The stored character is not shifted into a shift register until this shift register is being emptied. Until the time at which the character is transferred to the transmission shift register, the processor unit has to store a further character in the hold register, in order to guarantee further operation at full speed, in order to make it possible to transfer this further character directly from the hold register to the transmission shift register, if necessary. On the other hand, during reception, one bit is in each case transferred into the reception shift register. If a complete character is received, then it is transferred from the reception shift register to a hold register. The character then can be read by the processor unit from the reception shift register. If there are two or more received data items, then these data items are continuously shifted from the reception shift register to the hold register, which results in previous characters being overwritten in the hold register. If the processor unit has not yet read these previous characters, this data is lost.
In the case of buffered UART modules, the hold register that is used in unbuffered UART modules is replaced by a FIFO buffer (first-in-first-out buffer).
In contrast to unbuffered and buffered UART modules, DMA-UART modules use a DMA circuit arrangement which is integrated on a chip in order to transfer received data and data to be transmitted directly to the processor memory, without any action by the processor unit. It is thus possible to provide a very high performance level, with relatively little time being required for the processor unit. With this type of memory access, the task of the DMA module is thus to carry out the access process and to transfer the contents read from the memory via the system bus to other areas of the memory, or to peripheral modules. This procedure can be carried out more quickly than if the processor unit were itself to carry out the access and the transfer. In the case of a DMA-UART module, the processor unit only initiates the transfer via the DMA module.
The data to be transmitted or the data received is transmitted by means of communication protocols via the serial asynchronous interface or via the UART module. Communication protocols such as these include, for example, TCP/IP (Transfer Control Protocol/Internet Protocol), PPP (Point-to-Point Protocol), UDP (User Datagram Protocol), ICMP (Internet Control Message Protocol), IGP (Interior Gateway Protocol), EGP (Exterior Gateway Protocol), BGP (Border Gateway Protocol) etc.
More recent communication protocols for the serial asynchronous interface, such as the Bluetooth Standard 3-wire UART, use error identification and error correction algorithms for protection of the data communication, such as CRC (Cyclic Redundancy Check), and framing methods for synchronization, such as SLIP (Serial Line Internet Protocol). SLIP in this case denotes a protocol type that allows TCP and IP protocols to be transmitted via serial lines.
The conventional implementation of a UART interface or of a UART module is based on the use of a standard module or a standard IP that converts characters received in parallel form to serial, bit-oriented data streams in accordance with the UART specification. The data is not changed in the process. In general, the CRC checksums and the SLIP coding must be carried out by software or by means of a separate hardware module.
FIG. 1 illustrates one known implementation by means of software. FIG. 1 shows a processor unit PE which is electrically connected for data interchange purposes via an address bus AB and a data bus DB to one or more memory modules SP, for example RAM and/or ROM modules, and to a UART module. The UART module has a storage register SR, for example a FIFO storage register, and a monitoring unit SIE (Serial Interface Engine). The monitoring unit SIE checks the communication protocol (which is used for the data to be transmitted or the data received) for the asynchronous interface (physical layer), and is electrically connected to the storage register SR for data interchange purposes. In this software-based implementation of the UART interface, the code conversion and calculation of the CRC checksum involve a relatively high degree of software complexity. The code conversion and calculation of the CRC checksum must be carried out by the processor unit PE. Furthermore, it is impossible to use DMA controllers or DMA modules since, in this case, each individual byte must be processed.
The hardware-based implementation is illustrated in FIG. 2. In addition to the embodiment shown in FIG. 1, a DMA module in FIG. 2 is electrically connected to the address bus AB and to the data bus DB in order to interchange data with other modules on the chip or in the integrated circuit. Furthermore, this hardware-based implementation of a UART interface has a separate hardware module SHB. This separate hardware module SHB has a CRC unit for error identification and error correction, and a coding/decoding unit KE/DE. This known hardware-based embodiment of the UART interface can admittedly be implemented without any software complexity, but requires additional hardware components in the system. Particularly in the case of the illustrated embodiment with a DMA module, two channels must, however, be used for each transmission direction. One channel is in this case required for the data transfer from the memory SP to the units CRC and KE/DE, which are arranged in the separate hardware module SHB, and one channel is required for the data transfer from the separate hardware module SHB to the UART module.
The required complexity is relatively high both for the known software-based embodiment and for the known hardware-based embodiment. On the one hand, complex software is required, and on the other hand additional hardware modules and channels are required for the data transfer between the individual modules.